The present invention relates to semiconductor devices and methods of manufacture, and more particularly to a method for manufacturing an improved metal oxide semiconductor (MOS) transistor having a thin channel.
Field effect transistors (FETs) are the basic building block of today's integrated circuits. Such transistors can be formed in conventional substrates (such as silicon) or in the SOI layer of a silicon-on-insulator (SOI) substrate.
In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device, while maintaining the device's electrical properties. Additionally, all dimensions, of the device must be scaled simultaneously in order to optimize electrical performance of a device.
Thin channel silicon-on-insulator (SOI) devices having a thickness of about 50 nm or less are a promising option to further continue SOI complementary metal oxide semiconductor (CMOS) device scaling. Thin silicon channel devices provide a sharper-sub-threshold slope (measure of the abruptness of the switching of the device), high mobility (because the device is operated at a lower effective field) and better short channel effect control.
A disadvantage of thin silicon channel devices is that as the silicon-on-insulator (SOI) film is thinned the series resistance increases. One solution to the increasing series resistance inherent in thin channel devices is the use of an elevated source/drain region that may be formed by selective epitaxial Si growth.
In prior art thin channel devices, the extension implants are implanted prior to the formation of the raised source/drain regions; creating at least the following problems. First, by implanting the thin Si layer with a high dose/high energy implant, the Si crystal layer may be amorphized. Additionally, during activation of the source/drain regions, the anneal processing step causes recrystallization of the amorphous layer, which may result in the formation of polysilicon and the formation of defects to the extension region resulting in a higher resistivity. In addition, it is also difficult to clean the surfaces since p-type regions are formed due to electrochemical reactions where the p-type material has a greater affinity for oxide material. Epitaxial growth requires a clean surface having a substantial crystalline structure. Another problem with growing selective epitaxial Si on doped surfaces is that there is a significant difference in the thickness grown as a function of time for p-type Si compared to n-type Si. The thickness depends not only on the dopant type but also on the amount of dopant. The thickness of epitaxial silicon is difficult to control in a high volume manufacturing environment.
Prior art process schemes directed toward overcoming the thermal budget and growing epitaxial silicon on doped surfaces include a disposable spacer approach, which is complex and cost inefficient. More specifically, in some prior art thin channel devices a wide disposable spacer is utilized to grow the raised source/drain regions. High-energy implants are then conducted to form deep source/drain regions. Following the implants, the wide disposable spacer is removed and the extension regions are formed. A wide spacer is typically used to form the raised source/drain implants. Thus, the Si region under the spacer is of appreciable dimension and is at least as thin as the channel region. Therefore, the above described prior art process does not overcome the problem of the high resistance region outside the raised source/drain area.
In view of the state of the art mentioned above, it would be highly desirable to provide a method for forming thin channel silicon-on-insulator devices that overcome the above described disadvantages in conventional processing